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KAD2710L 300 unicorn park dr., woburn, ma 01801 sales: 1-781-497-0060 sales@kenetinc.com femtocharge is a registered trademark of kenet, inc. copyright ? 2007, kenet, inc. rev 1.1 page 1 of 17 description the kenet KAD2710L is the industry?s lowest power, 10-bit, high performance analog-to-digital converter. the converter ru ns at sampling rates up to 275msps, and is fabricated with kenet?s proprietary femtocharge? cmos technology. users can now obtain industry-leading snr and sfdr specifications while nearly halving power consumption. sampling rates of 210, 170 and 105msps are also available in the same pin- compatible package and in versions with 8-bit resolution. kenet?s kad2710c offers this performance with lvcmos outputs. all are available in 68-pin rohs-compliant qfn packages with exposed paddle. performance is specified over the full industrial temperature range (-40 to +85c). key specifications ? snr of 56db at nyquist ? sfdr of 71dbc at nyquist ? power consumption 280mw at f s = 275msps features ? on-chip reference ? internal track and hold ? 1.5v pp differential input voltage ? 600mhz analog input bandwidth ? two?s complement or binary output ? over-range indicator ? selectable 2 clock input ? lvds compatible outputs applications ? high-performance data acquisition ? portable oscilloscope ? medical imaging ? cable head ends ? power-amplifier linearization ? radar and satellite antenna array processing ? broadband communications ? local multipoint distribution system (lmds) ? communications test equipment 10-bit, 275msps analog-to-digital converter resolution, speed lvds outputs lvcmos outputs 10 bits 275msps KAD2710L-27 kad2710c-27 8 bits 275msps kad2708l-27 kad2708c-27 10 bits 210msps KAD2710L-21 kad2710c-21 8 bits 210msps kad2708l-21 kad2708c-21 10 bits 170msps KAD2710L-17 kad2710c-17 8 bits 170msps kad2708l-17 kad2708c-17 10 bits 105msps KAD2710L-10 kad2710c-10 8 bits 105msps kad2708l-10 kad2708c-10 table 1. pin-compatible products
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 2 of 17 absolute maximum ratings 1 1. exposing the device to levels in excess of the maximum ratings may cause permanent damage. exposure to maximum conditions for extended periods may affect device reliability. thermal impedance 2. paddle soldered to ground plane. esd electrostatic charge accumulates on humans, tools and equipment, and may discharge through any metallic package contacts (pins, ba lls, exposed paddle, etc.) of an integrated circuit. industry-standard protection techniques have been utilized in the design of this prod- uct. however, reasonable care must be taken in the storage and handling of esd sensitive products. contact kenet for the specific esd sensitivity rating of this product. parameter min max unit avdd2 to avss -0.4 2.1 v ovdd2 to ovss -0.4 2.1 v analog inputs to avss -0.4 avdd3 + 0.3 v clock inputs to avss -0.4 avdd2 + 0.3 v logic inputs to avss (vrefsel, clkdiv) -0.4 avdd3 + 0.3 v logic inputs to ovss (rst, 2sc) -0.4 ovdd2 + 0.3 v operating temperature -40 85 c storage temperature -65 150 c junction temperature 150 c avdd3 to avss -0.4 3.7 v logic output currents 10 ma lvds output currents 20 ma vref to avss -0.4 avdd3 + 0.3 v analog output currents 10 ma parameter symbol typ unit junction to paddle 2 jp 30 c/w
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 3 of 17 electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd2 = 1.8v, avdd3 = 3.3v, ovdd = 1.8v. t a = -40 c to +85 c, typ values at 25 c. f sample = 275msps, f in = nyquist. dc specifications parameter symbol conditions min typ max units power requirements 1.8v analog supply voltage avdd2 1.7 1.8 1.9 v 3.3v analog supply voltage avdd3 3.15 3.3 3.45 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 v 1.8v analog supply current i avdd2 44 ma 3.3v analog supply current i avdd3 41 ma 1.8v output supply current i ovdd 36 ma power dissipation p d 279 mw
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 4 of 17 analog specifications ac specifications parameter symbol conditions min typ max units analog input full-scale differential analog input voltage v in 1.4 1.5 1.6 v pp gain temperature coefficient a vtc full temp 90 ppm/oc full power bandwidth fpbw 600 mhz clock input sampling clock frequency range f sample 50 275 mhz clkp, clkn p-p differential input voltage v cdi 0.5 1.8 v pp clkp, clkn differential input resistance r cdi 10 m ? clkp, clkn common-mode input voltage v cci 0.9 v reference internal reference voltage v ref 1.18 1.21 1.24 v reference voltage temperature coefficient v rtc full temp 38 ppm/c common-mode output voltage v cm 0.86 v parameter symbol conditions min typ max units signal to noise ratio snr full temp 53 56 db signal to noise and distortion sinad full temp 52 55 db effective number of bits enob full temp 8.3 8.8 bits spurious free dynamic range sfdr full temp 62 71 dbc two-tone sfdr 2tsfdr f 1 =133mhz, f 2 =135mhz 70 dbc differential nonlinearity dnl no missing codes. -1 0.8 1.5 lsb power supply rejection ratio psrr 42 66 db word error rate wer 1x10 -12 integral nonlinearity inl -1.00 0.50 1.25 lsb
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 5 of 17 digital specifications parameter symbol conditions min typ max units inputs high input voltage (vrefsel) vrefsel v ih 0.8*avdd3 v low input voltage (vrefsel) vrefsel v il 0.2*avdd3 v input current high (vrefsel) vrefsel i ih vin = avdd3 0 1 10 a input current low (vrefsel) vrefsel i il vin = avss 25 65 75 a high input voltage (clkdiv) clkdiv v ih 0.8*avdd3 v low input voltage (clkdiv) clkdiv v il 0.2*avdd3 v input current high (clkdiv) clkdiv i ih vin = avdd3 25 65 75 a input current low (clkdiv) clkdiv i il vin = avss 0 1 10 a high input voltage (rst,2sc) rst,2sc v ih 0.8*ovdd2 v low input voltage (rst,2sc) rst,2sc v il 0.2*ovdd2 v input current high (rst,2sc) rst,2sc i ih vin = ovdd 0 1 10 a input current low (rst,2sc) rst,2sc i il vin = ovss 25 50 75 a input capacitance c di 3 pf lvds outputs differential output voltage v t 210 mv output offset voltage v os 1.15 v output rise time t r 500 ps output fall time t f 500 ps
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 6 of 17 timing diagram figure 1. lvds timing diagram timing specifications parameter symbol min typ max units aperture delay t a 1.7 ns rms aperture jitter j a 200 fs input clock to data propagation delay t pd 1.8 ns input clock to output clock propagation delay t cpd 1.3 ns output clock to data propagation delay t dc 470 ps output data to output clock setup time t su 3 ns output clock to output data hold time t h 75 ps latency (pipeline delay) l 28 cycles over voltage recovery t ovr 1 cycle
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 7 of 17 pin descriptions pin # name function 1, 14, 18, 20 avdd2 1.8v analog supply 2, 7, 10, 19, 21, 24 avss analog supply return 3 vref reference voltage out/in 4 vrefsel reference voltage select (0:int 1:ext) 5 vcm common mode voltage output 6, 15, 16, 25 avdd3 3.3v analog supply 8, 9 inp, inn analog input positive, negative 11-13, 29-32, 62, 63, 67 dnc do not connect 17 clkdiv clock divide by two (active low) 22, 23 clkn, clkp clock input complement, true 26, 45, 61 ovss output supply return 27, 41, 44, 60 ovdd2 1.8v lvds supply 28 rst power on reset (active low) 33, 34 d0n, d0p lvds bit 0 (lsb) output complement, true 35, 36 d1n, d1p lvds bit 1 output complement, true 37, 38 d2n, d2p lvds bit 2 output complement, true 39, 40 d3n, d3p lvds bit 3 output complement, true 42, 43 clkoutn, clkoutp lvds clock output complement, true 46, 47 d4n, d4p lvds bit 4 output complement, true 48, 49 d5n, d5p lvds bit 5 output complement, true 50, 51 d6n, d6p lvds bit 6 output complement, true 52, 53 d7n, d7p lvds bit 7 output complement, true 54, 55 d8n, d8p lvds bit 8 output complement, true 56, 57 d9n, d9p lvds bit 9 (msb) output complement, true 58, 59 orn, orp over range complement, true 64-66 connect to ovdd2 68 2sc two?s complement select (active low) exposed paddle avss analog supply return
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 8 of 17 pin configuration figure 2. pin configuration 2sc dnc ovdd2 ovdd2 ovdd2 dnc dnc ovss ovdd2 orp orn d9p d9n d8p d8n d7p d7n avdd2 avss avdd2 avss clkn clkp avss avdd3 ovss ovdd2 rst dnc dnc dnc dnc d0n d0p avdd2 avss vref vrefsel vcm avdd3 avss inp inn avss dnc dnc dnc avdd2 avdd3 avdd3 clkdiv top view not to scale d4p d4n ovss ovdd2 clkoutp clkoutn ovdd2 d3p d3n d2p d2n d1p d1n d6p d6n d5p d5n 68 qfn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 9 of 17 -95 -90 -85 -80 -75 -70 -65 -60 50 100 150 200 250 300 f sample (f s ) (mhz) hd2, hd3 (dbc ) -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -30 -25 -20 -15 -10 -5 0 analog input amplitude (v in ) (dbfs) hd2, hd3 (dbc ) typical operating characteristics avdd3=3.3v, avdd2=ovdd2 =1.8v, t ambient (t a )=25c, f sample =275mhz, v in = 6.865mhz @ -0.5dbfs unless noted. figure 3. snr vs. vin figure 4. sfdr vs. vin figure 5. hd2, 3 vs. vin figure 6. power dissipation vs. f sample figure 7. snr vs. f sample figure 8. hd2, 3 vs. f sample hd3 hd2 hd3 hd2 25 30 35 40 45 50 55 60 -30 -25 -20 -15 -10 -5 0 analog input amplitude (v in ) (dbfs) snr (db) 40 45 50 55 60 65 70 75 -30 -25 -20 -15 -10 -5 0 analog input amplitude (v in ) (dbfs) sfdr (dbc ) 140 160 180 200 220 240 260 280 300 50 100 150 200 250 300 f sample (f s ) (mhz) power dissipation (p d ) (mw) 55 55.2 55.4 55.6 55.8 56 56.2 56.4 56.6 56.8 57 50 100 150 200 250 300 f sample (f s ) (mhz) snr (db)
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 10 of 17 avdd3=3.3v, avdd2=ovdd2 =1.8v, t ambient (t a )=25c, f sample =275mhz, v in = 6.865mhz @ -0.5dbfs unless noted. figure 9. sfdr vs. f sample figure 10. differential nonlinearity vs. output code figure 11. integral nonlinearity vs. ou tput code figure 12. noise histogram figure 13. output spectrum at 6.865mhz figure 14. output spectrum at 68.465mhz 0 20 40 60 80 100 120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 x: 75.52 y: -70.83 frequency (mhz) amplitude (db) vin = -0.39dbfs snr = 56.1db sfdr = 70.5dbc sinad = 55.62db hd2 = -72.2dbc hd3 = -71.6dbc 0 20 40 60 80 100 120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (mhz) amplitude (db) vin = -0.34dbfs snr = 56.1db sfdr = 70.5dbc sinad = 55.8db hd2 = -91.8dbc hd3 = -70.5dbc 508 509 510 511 512 513 514 0 5,000 10,000 15,000 20,000 25,000 30,000 code code counts 0 128 256 384 512 640 768 896 1023 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 code inl (lsbs) 0 128 256 384 512 640 768 896 1023 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 code dnl (lsbs) 65 66 67 68 69 70 71 72 73 74 75 50 100 150 200 250 300 f sample (f s ) (mhz) sfdr (db)
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 11 of 17 avdd3 = 3.3v, avdd2=ovdd2 = 1.8v, t ambient (t a ) = 25c, f sample = 275mhz unless noted. figure 15. output spectrum at 130.565mhz figure 16. output spectrum at 143.155mhz figure 17. output spectrum at 492.965mhz 0 20 40 60 80 100 120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (mhz) amplitude (db ) vin = -0.39dbfs snr = 55.8dn sfdr = 68.9dbc sinad = 55.5db hd2 = -87.5dbc hd3 = -68.9dbc 0 20 40 60 80 100 120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (mhz) amplitude (db) vin = -0.41dbfs snr = 56.0db sfdr = 70.9dbc sinad = 55.7db hd2 = -79.8dbc hd3 = -70.8dbc 0 20 40 60 80 100 120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (mhz) amplitude (db) vin = -0.36dbfs snr = 54.1db sfdr = 56.6dbc sinad = 51.6db hd2 = -56.6dbc hd3 = -62.2dbc
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 12 of 17 functional description the kad2710 is based upon a ten bit, 275msps a/d converter in a pipelined architecture. the input volt- age is captured by a sample & hold circuit and con- verted to a unit of char ge. proprietary charge do- main techniques are used to compare the input to a series of reference charge s. these comparisons de- termine the digital code for each input value. the converter pipeline requires 24 sample clocks to pro- duce a result. digital error correction is also applied, resulting in a total latency of 28 clock cycles. this is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. at start-up, a self-calibration is performed to minimize gain and offset errors. the reset pin (rst) is initially held low internally at power-up and will remain in that state until the calibration is complete. the clock frequency should remain fixed during this time. calibration accuracy is maintained for the sample rate at which it is performed, and therefore should be repeated if the clock frequency is changed by more than 10%. recalibration can be initiated via the rst pin, or power cycling, at any time. reset the KAD2710L resets and calibrates automatically on power-up. to force a reset and initiate recalibration of the adc after power-up, connect an open-drain output device to drive pin 28 (rst) and pull low for at least ten sample clock periods. do not use a device with a pull-up on the reset pin, as it may prevent the kad2710 from properly executing the power-on re- set. voltage reference the vref pin is the full-scale reference, which sets the full-scale input voltage for the chip and requires a bypass capacitor of 0.1uf or larger. an internally generated reference voltag e is provided from a bandgap voltage buffer. this buffer can sink or source up to 50a externally. an external voltage may be applied to this pin to provide a more accurate reference than the inter- nally generated bandgap voltage or to match the full-scale reference among a system of KAD2710L chips. one option in the la tter configuration is to use one KAD2710L's internally generated reference as the external reference voltage for the other chips in the system. additionally, an externally provided refer- ence can be changed from the nominal value to adjust the full-scale input voltage within a limited range. to select whether the full-scale reference is internally generated or externally provided, the digital input port vrefsel should be set appropriately, low for in- ternal or high for external. this pin also has an internal 18k ? pull-up resistor. to use the internally generated reference vrefsel can be tied directly to avss, and to use an external reference vrefsel can be allowed to float. analog input the fully differential adc input (inp/inn) connects to the sample and hold circuit. the ideal full-scale input voltage is 1.5v pp , centered at the vcm voltage of 0.86v as shown in figure 18. figure 18. analog input range best performance is obtained when the analog in- puts are driven differentially in an ac-coupled con- figuration. the common mode output voltage, vcm, should be used to properly bias each input as shown in figures 19 and 20. an rf transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (if) inputs. the recommended biasing is shown in figure 19. figure 19. transformer input
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 13 of 17 the value of the shunt resistor should be determined based on the desired termination impedance. the differential input impedance of the kad2710 is 10m ? . a differential amplifier can be used in applications that require dc coupling, at the expense of reduced dynamic performance. in this configuration the am- plifier will typically reduce the achievable snr and distortion performance. a typical differential amplifier configuration is shown in figure 20. figure 20. differential amplifier input clock input the clock input circuit is a differential pair (see figure 24). driving these inputs with a high level (up to 1.8v pp on each input) sine or square wave will provide the lowest jitter performance. the recommended drive circuit is shown in figure 21. the clock inputs can be driven single-ended, but this is not recommended as performance will suffer. figure 21. recommended clock drive the clkdiv pin is a 1.8v cmos control pin (input) that selects whether the input clock frequency is passed directly to the adc or divided by two. apply- ing a low level will divide by two; 1.8v applied (or left floating) will not divide. use of the clock divider is optional. the KAD2710L's adc requires a clock with 50% duty cycle for opti- mum performance. if such a clock is not available, one option is to generate twice the desired sampling rate, then use the KAD2710L's divide-by-2 to generate a 50%-duty-cycle clock. the divider only uses the ris- ing edge of the clock, so 50% clock duty cycle is as- sured . table 3. clkdiv pin settings jitter in a sampled data system, clock jitter directly im- pacts the achievable snr performance. the theoreti- cal relationship between clock jitter and maximum snr is shown in equation 1 and is illustrated in figure 22. where tj is the rms uncertainty in the sampling instant . equation 1. this relationship shows the snr that would be achieved if clock jitter were the only non-ideal fac- tor. in reality, achievable snr is limited by internal factors such as dc linearity (dnl), aperture jitter and thermal noise. figure 22. snr vs. clock jitter any internal aperture jitter combines with the input clock jitter, in a root-sum-square fashion since they are not statistically correlated, and this determines the total jitter in the system. the total jitter, combined with other noise sources, then determines the achiev- able snr. clkdiv pin divide ratio avss 2 avdd 1 ? ? ? ? ? ? ? ? = j in t f snr 2 1 log 20 10 tj=100ps tj=10ps tj=1ps tj=0.1ps 10 bits 12 bits 14 bits 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 input frequency - mhz snr - db
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 14 of 17 equivalent circuits figure 23. analog inputs figure 24. clock inputs figure 25. lvds outputs layout considerations split ground and power planes data converters operating at high sampling frequen- cies require extra care in pc board layout. many complex board designs benefit from isolating the analog and digital sections. analog supply and ground planes should be laid out under signal and clock inputs. locate the digital planes under outputs and logic pins. grounds should be joined under the chip. clock input considerations use matched transmission lines to the inputs for the analog input and clock sign als. locate transformers, drivers and terminations as close to the chip as possi- ble. bypass and filtering bulk capacitors should have low equivalent series re- sistance. tantalum is a g ood choice. for best per- formance, keep ceramic bypass capacitors very close to device pins. longer traces will increase in- ductance, resulting in diminished dynamic perform- ance and accuracy. make sure that connections to ground are direct and low impedance. avoid form- ing ground loops. lvds outputs output traces and connections must be designed for 50 ? (100 ? differential) characteristic impedance. keep traces direct, and minimize bends where possi- ble. avoid crossing ground and power plane breaks with signal traces. unused inputs three of the four standard logic inputs (reset, clkdiv, 2sc) which will not be op erated do not require con- nection for best adc performance. these inputs can be left open if they are not used. vrefsel must be held low for internal reference, but can be left open for external reference. d[9:0]p ovdd ovdd 2ma or 3ma 2ma or 3ma data data data data d[9:0]n ovdd
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 15 of 17 definitions analog input bandwidth is the analog input fre- quency at which the spectral output power at the fundamental frequency (as determined by fft analy- sis) is reduced by 3db from its full-scale low-frequency value. this is also referred to as full power bandwidth. aperture delay or sampling delay is the time re- quired after the rise of the clock input for the sam- pling switch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. differential non-linearity (dnl) is the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternate method of specifying signal to noise-and-distortion ratio (sinad). in db, it is calculated as: enob = (sinad-1.76) / 6.02. integral non-linearity (inl) is the deviation of each individual code from a line drawn from negative full- scale (1/2 lsb below the first code transition) through positive full-scale (1/2 lsb above the last code transi- tion). the deviation of any given code from this line is measured from the center of that code. least significant bit (lsb) is the bit that has the small- est value or weight in a digital word. its value in terms of input voltage is vfs/(2n-1) where n is the resolution in bits. missing codes are output codes that are skipped and will never appear at the adc output. these codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. its value in terms of input voltage is vfs/2. pipeline delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the corresponding data. power supply rejection ratio (psrr) is the ratio of a change in power supply voltage to the input voltage necessary to negate the re sultant change in output code. signal to noise-and-distortion (sinad) is the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below one half the clock frequency, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) is the ratio of the rms signal amplitude to the sum of all other spectral components below one-half the sampling frequency, excluding harmonics and dc. spurious-free-dynamic range (sfdr) is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spuri- ous spectral component may or may not be a har- monic. two-tone sfdr is the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product.
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 16 of 17 e1 e d d1 d/2 d1/2 e1/2 e/2 0.80 dia pin 1 id terminal tip e c c section ?c-c? scale: none b a1 top view seating plane 4x p 0.45 0.25 min l e2/2 e2 16xe ref. e 16xe ref. 0.25 min bottom view 4x p b d2 d2/2 a a1 outline dimensions
KAD2710L 10-bit, 275msps analog-to-digital converter rev 1.1 page 17 of 17 package dimensions (mm) ordering guide this product is compliant with eu directive 2002 /95/ec regarding the restriction of hazardous sub- stances (rohs). contact kenet for a materials declaration for this product. ref min nom max note a - 0.90 1.00 a1 0.00 0.01 0.05 per jedec mo-220 b 0.18 0.23 0.30 measured between 0.20 and 0.25mm from plated terminal tip d 10.00 bsc d1 9.75 bsc d2 7.55 7.70 7.85 e 0.50 bsc e 10.00 bsc e1 9.75 bsc e2 7.55 7.70 7.85 l 0.50 0.60 0.65 n 68 total terminals n d 17 terminals in d (x) direction n e 17 terminals in e (y) direction 0 12? p 0 0.42 0.60 model speed package temp. range KAD2710L-27q68 275msps 68-qfn ep -40c to +85c KAD2710L-21q68 210msps 68-qfn ep -40c to +85c KAD2710L-17q68 170msps 68-qfn ep -40c to +85c KAD2710L-10q68 105msps 68-qfn ep -40c to +85c rohs

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